Undoubtedly, the future computing platform for SQL Server and other major database and server products is a 64-bit product running on the x64 platform. Adoption of this technology lies in the greater addressable memory the x64 64-bit architecture offers. Database systems can use this additional addressable memory to expand the buffer cache, procedure cache, and working storage, thus reducing disk I/O and resulting in vastly improved performance. Microsoft's decision to move the next release of Exchange to 64-bit—completely dropping the 32-bit version of the product—is proof that Microsoft sees the x64 platform as the architecture of the future.
There are two versions of the x64 architecture. Both the AMD Opteron and the Intel EM64T processors are x64 compatible and capable of running 32-bit x86 and 64-bit x64 applications at full speed. In April 2003, AMD released the Opteron, which uses the new x64 architecture and is fully 32-bit x86 binary compatible. Intel realized the market was not going to adopt its proprietary Itanium processor and followed AMD's lead by releasing its own x64-compatible XEON EM64T processors in October 2005.The Intel EM64T processor is the direct competition to AMDs Opteron processor. However, you'll find significant differences between the processors and the system architectures they use.
One important difference between AMD and Intel x64 processors lies in the memory addressability of each processor. The AMD Opteron line of processors uses a 40-bit physical address space, allowing the Opteron to address a maximum of 1TB of RAM. Intel EM64T processors are derived from Intel's 32-bit line of processors and use a smaller, 36-bit physical address, which limits the maximum amount of addressable RAM to 64GB. Another significant difference is in the system designs that the two processors use. The Intel EM64T line of processors uses an older, front-side bus design. The front-side bus is the physical pathway that connects the system's processors and memory through a shared memory controller. This design limits scalability because the total bandwidth of the front-side bus is split between all of the processors using the system. As more processors are added, the front-side bus bandwidth is further divided between the processors. Overall system performance is limited more by the speed of the frontside bus than by the speed of the CPUs.
In contrast, the AMD Opteron uses the new HyperTransport bus. The HyperTransport bus design utilizes an integrated memory controller on the CPUs. Each CPU has its own direct connection to the system RAM, and utilizes an 8GBps connection between CPUs and between the CPUs and system I/O devices. This design is more scalable than the Intel design because it avoids a single system bottleneck. As more CPUs are added to this design, the overall bandwidth of the system actually increases because each CPU has its own memory connection. The HyperTransport bus is 128 bits wide versus the 64-bit EM64T bus. The RAM, I/O, and system devices don't compete for bandwidth in a HyperTransport system design. This design eliminates contention for available bandwidth and reduces latency. The HyperTransport technology supports up to three direct 8GBps CPU connections providing up to 24GBps peak bandwidth per processor. The result of the AMD architecture is improved system scalability and performance.
