R10000 Design Innovations

  • Floating-point processing done on one chip

  • Ability to process up to four instructions out of order to any two-integer, two-floating-point, one-load/store unit

  • Dynamic register renaming which allows speculative execution of predicted branches using "false" registers which can later be kept or discarded

  • On-chip instruction cache which enables partial decoding of instructions when they are loaded from memory into cache
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